Difference between revisions of "John Backes"

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==About John==
 
==About John==
  
My research interests include logic synthesis, formal verification, technology mapping, and SAT-based algorithms.
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I completed my Ph.D. under [[Marc Riedel | Prof. Marc Riedel]] in 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at [http://www.rockwellcollins.com/ Rockwell Collins]
  
 
== John's Papers ==
 
== John's Papers ==
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'''Dissertation'''
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{|
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{| style="background:#F0E68C"
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|- valign=top
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|  width="100" | '''title''':
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|  width="500" | [[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf |Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability]]
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|-
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| '''author''':
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| [[John Backes]]
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| '''Dissertation''':
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| Ph.D., [http://www.ece.umn.edu Electrical and Computer Engineering], [http://www.umn.edu University of Minnesota], 2013.
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|}
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| align=center width="70" |
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<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/9/96/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
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<br>[[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf | Paper]]
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| align=center width="70" |
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<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span>
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<br> [http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx Slides]
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'''Journal Papers'''
 
'''Journal Papers'''
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| [[John Backes]]  and [[Marc Riedel]]
 
| [[John Backes]]  and [[Marc Riedel]]
 
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| '''will&nbsp;appear&nbsp;in''':
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| '''appeared&nbsp;in''':
 
| [http://todaes.acm.org/ ACM Transactions on Design Automation of Electronic Systems], 2012.
 
| [http://todaes.acm.org/ ACM Transactions on Design Automation of Electronic Systems], 2012.
 
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<br>[[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf‎  | Paper]]
 
<br>[[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf‎  | Paper]]
 
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|}
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<br>[[Media:Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf  | Paper]]
 
<br>[[Media:Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf  | Paper]]
 
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Latest revision as of 17:28, 24 November 2015

John Backes.jpg

About John

I completed my Ph.D. under Prof. Marc Riedel in 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at Rockwell Collins

John's Papers

Dissertation

title: Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability
author: John Backes
Dissertation: Ph.D., Electrical and Computer Engineering, University of Minnesota, 2013.

Pdf.jpg
Paper

Ppt.jpg
Slides

Journal Papers

title: The Synthesis of Cyclic Dependencies with Boolean Satisfiability
authors: John Backes and Marc Riedel
appeared in: ACM Transactions on Design Automation of Electronic Systems, 2012.

Pdf.jpg
Paper

title: The Synthesis of Stochastic Circuits for Nanoscale Computation
authors: Weikang Qian, John Backes, and Marc Riedel
appeared in: International Journal of Nanotechnology and Molecular Computation,
vol. 1, no. 4, pp. 39–57, 2010.

Pdf.jpg
Paper

Conference Papers

title: Using Cubes of Non-state Variables With Property Directed Reachability
authors: John Backes and Marc Riedel
presented at: Design Automation & Test in Europe, Grenoble, France, 2013.

Pdf.jpg
Paper

Ppt.jpg
Poster

title: Resolution Proofs as a Data Structure For Logic Synthesis
authors: John Backes and Marc Riedel
presented at: The International Workshop on Logic Synthesis, La Jolla, CA, 2011.

Pdf.jpg
Paper

Ppt.jpg
Slides

title: Reduction of Interpolants For Logic Synthesis
authors: John Backes and Marc Riedel
presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2010.

Pdf.jpg
Paper

Ppt.jpg
Slides

title: The Synthesis of Cyclic Dependencies with Craig Interpolation
authors: John Backes and Marc Riedel
presented at: The International Workshop on Logic and Synthesis, Berkeley, CA, 2009.

Pdf.jpg
Paper

Ppt.jpg
Slides

title: The Analysis of Cyclic Circuits with Boolean Satisfiability
authors: John Backes, Brian Fett, and Marc Riedel
presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2008.

Pdf.jpg
Paper

Ppt.jpg
Slides

Contact Information

  • Email: BackesEmail.gif
  • Phone: (952) 239-7828