Difference between revisions of "John Backes"

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(John's Papers)
(John's Papers)
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|  width="100" | '''title''':
 
|  width="100" | '''title''':
|  width="507" | [[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf‎‎‎ | Resolution Proofs as a Data Structure For Logic Synthesis]]
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|  width="550" | [[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf‎‎‎ | Resolution Proofs as a Data Structure For Logic Synthesis]]
 
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| '''authors''':
 
| '''authors''':
 
| John Backes and [[Marc Riedel]]
 
| John Backes and [[Marc Riedel]]
 
|-  
 
|-  
| '''to be presented at''':
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| '''to&nbsp;be&nbsp;<br \>presented&nbsp;at''':
 
| [http://iwls.org/ The International Workshop On Logic Syntehsis], San Diego, CA, 2011.
 
| [http://iwls.org/ The International Workshop On Logic Syntehsis], San Diego, CA, 2011.
 
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Revision as of 15:31, 3 May 2011

John Backes.jpg

About John

My research interests include logic synthesis, formal verification, technology mapping, and SAT-based algorithms.

John's Papers

Journal Papers

title: The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability
authors: John Backes, Brian Fett and Marc Riedel
submitted to: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010.
       

Pdf.jpg
Paper

title: The Synthesis of Stochastic Circuits for Nanoscale Computation
authors: Weikang Qian, John Backes, and Marc Riedel
presented at: International Journal of Nanotechnology and Molecular Computation, 2010.
       

Pdf.jpg
Paper

       

Ppt.jpg
Slides

Conference Papers

title: Resolution Proofs as a Data Structure For Logic Synthesis
authors: John Backes and Marc Riedel
to be 
presented at
:
The International Workshop On Logic Syntehsis, San Diego, CA, 2011.
       

Pdf.jpg
Paper

       
title: Reduction of Interpolants For Logic Synthesis
authors: John Backes and Marc Riedel
presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2010.
presented at: International Workshop on Logic and Synthesis, Irvine, CA, 2010.
       

Pdf.jpg
Paper

       

Ppt.jpg
Slides

title: The Synthesis of Cyclic Dependencies with Craig Interpolation
authors: John Backes and Marc Riedel
presented at: International Workshop on Logic and Synthesis, Berkeley, CA, 2009.
       

Pdf.jpg
Paper

       

Ppt.jpg
Slides

title: The Analysis of Cyclic Circuits with Boolean Satisfiability
authors: John Backes, Brian Fett and Marc Riedel
presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2008.
       

Pdf.jpg
Paper

       

Ppt.jpg
Slides

Contact Information

  • Email: BackesEmail.gif
  • Phone: (952) 239-7828