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<p><span dir="auto"><span class="autocomment">John's Papers</span></span></p>
<p><b>New page</b></p><div>[[Image:John_Backes.jpg|200px]]<br />
<br />
==About John==<br />
<br />
I completed my Ph.D. under [[Marc Riedel | Prof. Marc Riedel]] in 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at [http://www.rockwellcollins.com/ Rockwell Collins]<br />
<br />
== John's Papers ==<br />
<br />
'''Dissertation'''<br />
<br />
{|<br />
| rowspan=2 | <br />
{| style="background:#F0E68C"<br />
|- valign=top<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf |Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability]]<br />
|- <br />
| '''author''':<br />
| [[John Backes]]<br />
|- <br />
| '''Dissertation''':<br />
| Ph.D., [http://www.ece.umn.edu Electrical and Computer Engineering], [http://www.umn.edu University of Minnesota], 2013. <br />
|}<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/9/96/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf | Paper]]<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span><br />
<br> [http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx Slides]<br />
|}<br />
<br />
'''Journal Papers'''<br />
<br />
{|<br />
| rowspan=2 | <br />
{| style="background:#F0E68C"<br />
|- valign=top<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf | The Synthesis of Cyclic Dependencies with Boolean Satisfiability]]<br />
|- <br />
| '''authors''':<br />
| [[John Backes]] and [[Marc Riedel]]<br />
|- <br />
| '''appeared&nbsp;in''':<br />
| [http://todaes.acm.org/ ACM Transactions on Design Automation of Electronic Systems], 2012.<br />
|}<br />
| align=center | <br />
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/d/df/Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf | Paper]]<br />
|}<br />
<!--<br />
{|<br />
|<br />
{| style="background:#F0E68C"<br />
|- valign="top"<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf | The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability]]<br />
|- valign="top"<br />
| '''authors''':<br />
| [[John Backes]], [[Brian Fett]], and [[Marc Riedel]]<br />
|- valign="top"<br />
| '''submitted&nbsp;to''':<br />
| [http://jsat.ewi.tudelft.nl/ Journal on Satisfiability, Boolean Modeling and Computation], 2011.<br />
|}<br />
| align=center | <br />
<span class="plainlinks"><br />
[http://www.mriedel.ece.umn.edu/wiki/images/6/66/Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf | Paper]]<br />
|}<br />
--><br />
{|<br />
|<br />
{| style="background:#F0E68C"<br />
|- valign="top"<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf | The Synthesis of Stochastic Circuits for Nanoscale Computation]]<br />
|- valign="top"<br />
| '''authors''':<br />
| [[Weikang Qian]], [[John Backes]], and [[Marc Riedel]]<br />
|- valign="top"<br />
| '''appeared&nbsp;in''':<br />
| [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description International Journal of Nanotechnology and Molecular Computation], <br>vol. 1, no. 4, pp. 39&ndash;57, 2010.<br />
|}<br />
| align=center width="70 | <br />
<span class="plainlinks">[http://cctbio.ece.umn.edu/wiki/images/a/a8/Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf | Paper]]<br />
|}<br />
<br />
'''Conference Papers'''<br />
<br />
{|<br />
<br />
| rowspan=2 | <br />
{| style="background:#F0E68C"<br />
|- valign=top<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf | Using Cubes of Non-state Variables With Property Directed Reachability]]<br />
|- <br />
| '''authors''':<br />
| [[John Backes]] and [[Marc Riedel]]<br />
|- <br />
| '''presented&nbsp;at''':<br />
| [http://www.date-conference.com/ Design Automation & Test in Europe], Grenoble, France, 2013.<br />
|}<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/c/c0/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf | Paper]]<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/4/41/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pptx http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span><br />
<br> [http://www.mriedel.ece.umn.edu/wiki/images/4/41/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pptx Poster]<br />
<br />
|}<br />
<br />
{|<br />
<br />
| rowspan=2 | <br />
{| style="background:#F0E68C"<br />
|- valign=top<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf | Resolution Proofs as a Data Structure For Logic Synthesis]]<br />
|- <br />
| '''authors''':<br />
| [[John Backes]] and [[Marc Riedel]]<br />
|- <br />
| '''presented&nbsp;at''':<br />
| [http://iwls.org/ The International Workshop on Logic Synthesis], La Jolla, CA, 2011.<br />
|}<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/2/27/Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf | Paper]]<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/5/5e/Iwls2011final_final.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span><br />
<br> [http://cctbio.ece.umn.edu/wiki/images/f/f1/Backes_Riedel_Resolution_Proofs_as_a_Data_Structure_for_Logic_Synthesis.ppt Slides]<br />
<br />
|}<br />
<br />
{|<br />
| <br />
{| style="background:#F0E68C"<br />
|- valign="top"<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf | Reduction of Interpolants For Logic Synthesis]]<br />
|- valign="top"<br />
| '''authors''':<br />
| [[John Backes]] and [[Marc Riedel]]<br />
|- valign="top"<br />
| '''presented&nbsp;at''':<br />
| [http://www.iccad.com The International Conference on Computer-Aided Design], San Jose, CA, 2010.<br />
|}<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://cadbio.com/wiki/images/b/b6/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf | Paper]]<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://cctbio.ece.umn.edu/wiki/images/0/00/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span><br />
<br> [http://cctbio.ece.umn.edu/wiki/images/0/00/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.ppt Slides]<br />
|}<br />
{|<br />
|<br />
{| style="background:#F0E68C"<br />
|- valign="top"<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf | The Synthesis of Cyclic Dependencies with Craig Interpolation]]<br />
|- valign="top" <br />
| '''authors''':<br />
| [[John Backes]] and [[Marc Riedel]]<br />
|- valign="top"<br />
| '''presented&nbsp;at''':<br />
| [http://www.sigda.org/iwls/iwls2009 The International Workshop on Logic and Synthesis], Berkeley, CA, 2009.<br />
|}<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://cctbio.ece.umn.edu/wiki/images/e/ec/Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf | Paper]]<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/a/ad/Backes_Riedel_The_Synthesis_Of_Functional_Dependencies_With_Craig_Interpolation.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span><br />
<br> [http://www.mriedel.ece.umn.edu/wiki/images/a/ad/Backes_Riedel_The_Synthesis_Of_Functional_Dependencies_With_Craig_Interpolation.ppt Slides]<br />
|}<br />
{|<br />
|<br />
{| style="background:#F0E68C"<br />
|- valign="top"<br />
| width="100" | '''title''':<br />
| width="500" | [[Media:Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf | The Analysis of Cyclic Circuits with Boolean Satisfiability]]<br />
|- valign="top"<br />
| '''authors''':<br />
| [[John Backes]], [[Brian Fett]], and [[Marc Riedel]]<br />
|- valign="top"<br />
| '''presented&nbsp;at''':<br />
| [http://www.iccad.com/events/eventdetails.aspx?id=86-2-B The International Conference on Computer-Aided Design], San Jose, CA, 2008.<br />
|}<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://cctbio.ece.umn.edu/wiki/images/8/84/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span><br />
<br>[[Media:Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf | Paper]]<br />
| align=center width="70" | <br />
<span class="plainlinks">[http://cctbio.ece.umn.edu/files/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span><br />
<br> [http://cctbio.ece.umn.edu/files/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.ppt Slides]<br />
|}<br />
<br />
== Contact Information ==<br />
<br />
* '''Email''': [[Image:BackesEmail.gif]]<br />
* '''Phone''': (952) 239-7828</div>
Student